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Integrated Circuit Systems, Inc.
ICS9148-111
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
Recommended Application: ALI (Aladdin V ) mobile. Output Features: * 3 - CPUs @ 2.5V/3.3V, up to 100MHz. * 3 - AGPCLK @ 3.3V * 13 - SDRAM @ 3.3V, up to 100MHz. * 6 - PCI @ 3.3V, including one free running. * 1 - 48MHz, @ 3.3V fixed. * 1 - REF @ 3.3V, 14.318MHz. Features: * Up to 100MHz frequency support * Support power management: CPU, PCI, AGP stop and, Power down Mode from I2C programming. * Spread spectrum for EMI control (0 to -0.6%, 0.25%). * Uses external 14.318MHz crystal * FS pins for frequency select Key Specifications: * CPU - CPU: <250ps * SDRAM - SDRAM: <250ps * AGP-AGP: <250ps * PCI - PCI: <500ps * CPU-SDRAM <500ps * CPU(early)-PCI: 1-4ns, Center 2-6ns * CPU-AGP <500ps
Pin Configuration
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Block Diagram
Functionality
CPU, PCI AGP FS2 FS1 FS0 SDRAM (MHz) (MHz) (MHz) 1 1 1 100 33.33 66.67 1 1 0 95.25 31.75 63.50 1 0 1 83.3 33.30 66.60 1 0 0 75 30.00 60.00 0 1 1 91.5 30.50 61.00 0 1 0 96.22 32.07 64.15 0 0 1 66.8 33.40 66.80 0 0 0 60 30.00 60.00 REF, IOAPIC (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
9148-111 Rev A 10/19/99 Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9148-111
Pin Configuration
PIN NUMBER 1 2 3,9,16,22,27, 33,39,45 4 5 6 7 FS11, 2 8 10, 11, 12, 13 14 15 17 PCICLK0 FS21, 2 PCICLK(1:4) VDD5 BUFFERIN CPU_STOP#1 SDRAM 11 18 28, 29, 31, 32, 34, 35,37,38 20 PCI_STOP#1 SDRAM 10 SDRAM (0:9) AGP_STOP# SDRAM9 21 19,30,36 23 24 25 MODE1, 2 48MHz 26 41, 43, 44 40 42 46, 47 48 FS01, 2 CPUCLK(0:3) SDRAM12 VDDL AGP (1:2) VDD4 IN OUT IN OUT OUT PWR OUT PWR PD# SDRAM8 VDD3 SDATA SCLK AGP0 IN OUT IN OUT PWR IN IN OUT IN OUT OUT IN OUT IN OUT PWR IN IN OUT P I N NA M E VDD1 REF0 C P U 3 . 3 # _ 2 . 5 1,2 GND X1 X2 VDD2 PCICLK_F TYPE PWR OUT IN PWR IN OUT PWR OUT DESCRIPTION Ref (0:2), XTAL power supply, nominal 3.3V 14.318 Mhz reference clock. Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V C P U 1. L a t c h e d i n p u t 2 Ground Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew (CPU early) This is not affected by PCI_STOP# Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Frequency select pin. Latched Input PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Supply for fixed PLL, 48MHz, AGP0 Input pin for SDRAM buffers. Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output SDRAM clock outputs. This asynchronous input halts AGP(1:2) clocks at logic "0" level when input low (in Mobile Mode, MODE=0) Does not affect AGP0 SDRAM clock output This asyncheronous Power Down input Stops the VCO, crystal & internal clocks when active, Low. (In Mobile Mode, MODE=0) SDRAM clock output Supply for SDRAM (0:11), CPU Core, 48MHz clocks, nominal 3.3V. Data input for I2C serial input. Clock input of I2C input Advanced Graphic Port output, powered by VDD4. Not affected by AGP_STOP# Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock for USB timing. Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Feedback SDRAM clock output. Supply for CPU (0:3), either 2.5V or 3.3V nominal Advanced Graphic Port outputs, powered by VDD4. Supply for AGP (0:2)
Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9148-111
General Description
The ICS9148-111 is a single chip clock solution for Desktop/ Notebook designs using the ALI (Aladdin V ) mobile style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9148-111 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:12), supply for PLL core VDD4 = AGP (1:2) VDD5 = Fixed PLL, 48MHz , AGP0 VDDL = CPUCLK (0:2)
Mode Pin - Power Management Input Control
MODE, Pin 25 (Latched Input) 0 1 Pin 17 CPU_STOP# (INPUT) SDRAM 11 (OUTPUT) Pin 18 PCI_STOP# (INPUT) SDRAM 10 (OUTPUT) Pin 20 AGP_STOP# (INPUT) SDRAM 9 (OUTPUT) Pin 21 PD# (INPUT) SDRAM 8 (OUTPUT)
Power Management Functionality
AGP_STOP# CPU_STOP# PCI_STOP# 1 1 1 0 0 1 1 1 1 1 0 1 AGP, CPUCLK Outputs Stopped Low Running Running Running PCICLK (0:5) Running Running Stopped Low Running PCICLK_F, REF, 48MHz and SDRAM Running Running Running Running Crystal OSC Running Running Running Running VCO Running Running Running Running AGP(1:2) Running Running Running Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5 Input level (Latched Data) 1 0 Buffer Selected for operation at: 2.5V VDD 3.3V VDD
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ICS9148-111
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9148-111
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit Bit 7
Bit 6:4
Bit 3 Bit 2 Bit 1 Bit 0
Description Must be 0 for normal operation 0 -- +/- 0.25% Spread Spectrum Modulation 1 -- +/- 0.6% Spread Spectrum Modulation Bit6 Bit5 Bit4 CPU Clock PCI 100 33.33 111 95.25 31.75 110 83.3 33.30 101 75 30.00 100 91.5 30.50 011 96.22 32.07 010 66.8 33.40 001 60 30.00 000 0 - Frequency is selected by hardware select, Latched inputs 1 - Frequency is selected by Bit 6:4 (above) Must be 0 for normal operation 0 - Spread Spectrum center spread type. 1 - Spread Spectrum down spread type. 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1 - Tristate all outputs
PWD 0 AGP 66.67 63.50 66.60 60.00 61.00 64.15 66.80 60.00
Note 1
0 0 0 0
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if bit 3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle.
Note: PWD = Power-Up Default
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 41 43 44 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) SDRAM12 (Act/Inact) (Reserved) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 13 12 11 10 8 PWD 1 1 1 1 1 1 1 1 Description (Reserved) PCICLK_F (Act/Inact) (Reserved) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0(Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
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ICS9148-111
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 34 35 37 38 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 (Act/Inact) SDRAM6 (Act/Inact) SDRAM5 (Act/Inact) SDRAM4 (Act/Inact) SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact)
Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 25 17 18 20 21 PWD 1 1 1 1 1 1 1 1 Description AGP0 (Active/Inactive) (Reserved) (Reserved) (Reserved) SDRAM11 (Act/Inact) (Desktop Mode Only) SDRAM10 (Act/Inact) (Desktop Mode Only) SDRAM9 (Act/Inact) SDRAM8 (Act/Inact)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 47 46 2 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) AGP1 (Act/Inact) (Reserved) (Reserved) AGP2 (Act/Inact) REF0 (Act/Inact)
Byte 6: Optional Register for Possible Furture Requirements
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Byte 6 is reserved by Integrated Circuit Systems for future applications.
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ICS9148-111
Shared Pin Operation Input/Output Pins
Pins 2, 7, 8, 25 & 26 on the ICS9148-111 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
Fig. 1
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ICS9148-111
Fig. 2a
Fig. 2b
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ICS9148-111
AGP_STOP# Timing Diagram
AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP clocks. for low power operation. AGP_STOP# is synchronized by the ICS9148-111. The AGPCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK and AGPCLK off latency is less than 4 AGPCLKs. This function is available only with MODE pin latched low.
Notes: 1. All timing is referenced to the internal CPUCLK. 2. AGP_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9148-111. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
5. Only applies if MODE pin latched 0 at power up.
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ICS9148-111
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9148-111. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9148-111. 3. All other clocks continue to run undisturbed. (including SDRAM outputs).
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ICS9148-111
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-111. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9148-111 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9148. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
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ICS9148-111
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148-111 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS9148-111
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD=3.3 V +\- 5%, VDDL = 2.5 V +/- 5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS VIH Input High Voltage VIL Input Low Voltage IIH VIN = VDD Input High Current VIN = 0 V; Inputs with no pull-up resistors IIL1 Input Low Current VIN = 0 V; Inputs with pull-up resistors IIL2 Input Low Current IDD3.3OP66 Select @ 66.8MHz; CL=0; all outputs running Operating IDD3.3OP100 Select @ 100MHz; CL=0; all outputs running Supply Current IDD3.3PD PD# = 0; Full capacitive loads Power down Current VDD = 3.3 V Fi Input frequency 1 CIN Logic Inputs Input Capacitance CINX X1 & X2 pins 1 TTrans To first crossing of target Freq. Transition Time 1 TS From first crossing to 1% of target Freq. Settling Time 1 TSTAB From VDD = 3.3 V to 1% target Freq. Clk Stabilization TCPU-PCI VT=1.5 V; f=66/100 MHz; VDD=VDDL 1 TCPU-PCI VT=1.5 V; f=83/75 MHz; VDD=VDDL Skew TAGP-PCI VT = 1.5 V; AGP leads 1 Guaranteed by design, not 100% tested in production. MIN 2 VSS-0.3 -5 -200 MAX UNITS VDD+0.3 V 0.8 V 0.1 5 A 2.0 A -100 A 115 160 mA 140 190 mA 150 600 A 14.318 16 MHz 5 pF 36 45 pF 0.65 2 ms 0.35 3 ms <1.5 2 ms 2.5 4 ns 4.25 5 ns 400 700 ps TYP
12 27
2 2
Electrical Characteristics - Input/Supply/Common Output Parameters
T A = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAM ETER Operating Supply Current
1
SYM BOL IDD2.5 OP66 IDD2.5 OP10 0
CONDITIONS Select @ 66.8M Hz; C L=0; all outputs running Select @ 100M Hz; C L=0; all outputs running
M IN
TYP 15 18
M AX 30 35
UNITS mA mA
Guaranteed by design, not 100% tested in production.
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ICS9148-111
Electrical Characteristics - CPU3.3
TA = 0 - 70 C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS IOH = -28 mA VOH2B Output High Voltage VOL2B IOL = 24 mA Output Low Voltage IOH2B VOH =2.0 V Output High Current VOL = 0.8 V IOL2B Output Low Current VOL = 0.4 V, VOH = 2.4 V Rise Time tr2B1 1 Fall Time tf2B VOH = 2.4 V, VOL = 0.4 V Duty Cycle dt2B1 VT = 1.5 V 1 Skew tsk2B VT = 1.5 V Jitter, Single Edge VT = 1.5 V; f=66/100 MHz tjsrd2B1 VT = 1.5 V; f=75/83 MHz Displacement2 1 Guaranteed by design, not 100% tested in production. 2 Edge displacement of a period relative to a 10-clock-cycle rolling average period. MIN 2.5 TYP 2.6 0.34 -29 52 1 0.9 52 90 150 285 MAX UNITS V 0.4 V -23 mA mA 2 ns 2 ns 55 % 175 ps 320 ps 550 ps
33
45
Electrical Characteristics - CPU2.5
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -8.0 mA 2 Output High Voltage VOH2B Output Low Voltage VOL2B IOL = 12 mA Output High Current IOH2B VOH =1.7 V Output Low Current IOL2B VOL = 0.7 V 19 1 Rise Time tr2B VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V Fall Time tf2B1 1 VT = 1.25 V 45 Duty Cycle dt2B 1 VT = 1.25 V Skew tsk2B Jitter, Single Edge tjsrd2B1 VT = 1.25 V; f=66/100 MHz 2 Displacement VT = 1.25 V; f=75/83 MHz
1 2
TYP 2.2 0.22 -20 39 1 0.9 51 110 170 310
MAX UNITS V 0.4 V -16 mA mA 1.6 ns 1.6 ns 55 % 175 ps 340 ps 680 ps
Guaranteed by design, not 100% tested in production. Edge displacement of a period relative to a 10-clock-cycle rolling average period.
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ICS9148-111
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN VOH1 IOH = -28 mA Output High Voltage 2.4 VOL1 IOL = 23 mA Output Low Voltage IOH1 VOH = 2.0 V Output High Current IOL1 VOL = 0.8 V Output Low Current 41 1 tr1 VOL = 0.4 V, VOH = 2.4 V Rise Time Fall Time1 Duty Cycle
1 1
TYP 3 0.32 -60 54 1.6 1.3 51 100 220
MAX UNITS V 0.4 V -40 mA mA 2 ns 2 55 250 500 ns % ps ps
tf1 dt1
VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V 45
tsk1 VT = 1.5 V Skew Jitter, Single Edge VT = 1.5 V tjsrd1 Displacement2 1 Guaranteed by design, not 100% tested in production. 2 Edge displacement of a period relative to a 10-clock-cycle rolling average period.
Electrical Characteristics - SDRAM
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -24 mA 2.4 Output High Voltage VOH3 Output Low Voltage VOL3 IOL = 23 mA Output High Current IOH3 VOH = 2.0 V Output Low Current IOL3 VOL = 0.8 V 41 Rise Time Tr31 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V Fall Time Tf31 1 VT = 1.5 V 48 Duty Cycle Dt3 VT = 1.5 V, Sdram 0,8,9,12 Window Tsk1 VT = 1.5 V, Sdram 2,4,5,6 Window Skew1 VT = 1.5 V, Sdram 1,3,7,10,11 Window Tprop VT = 1.5 V Propagation Delay
1
TYP 2.9 0.35 -68 53 1.4 1.4 54 140 120 140 3.5
MAX UNITS V 0.4 V -40 mA mA 2 ns 2 ns 60 % 250 4.5 ps ns
Guarenteed by design, not 100% tested in production.
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ICS9148-111
Electrical Characteristics - AGP
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH1 IOH = -28 mA 2.4 IOL = 23 mA Output Low Voltage VOL1 VOH = 2.0 V Output High Current IOH1 VOL = 0.8 V 41 Output Low Current IOL1 Rise Time1 Fall Time
1
TYP 3 0.32 -60 54 1.3 1.2 51 53 110 660 310
MAX UNITS V 0.4 V -40 mA mA 2 2 55 58 250 1200 650 ns ns % % ps ps ps
tr1 tf1 dt1 tsk1 tjsrd1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V, AGP0 VT = 1.5 V, AGP1:2 VT = 1.5 V VT = 1.5 V, AGP0 VT = 1.5 V, AGP1:2 45 48
Duty Cycle1 Skew1 Jitter, Single Edge Displacement2
1 2
Guaranteed by design, not 100% tested in production. Edge displacement of a period relative to a 10-clock-cycle rolling average period.
Electrical Characteristics - REF0, 48MHz
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -16 mA 2.4 Output High Voltage VOH5 Output Low Voltage VOL5 IOL = 9 mA VOH = 2.0 V Output High Current IOH5 Output Low Current IOL5 VOL = 0.8 V 16 Rise Time1 Fall Time1 Duty Cycle1 Jitter, Single Edge Displacement
2
TYP 2.6 0.24 -32 28 1.5 2.1
MAX UNITS V 0.4 V -22 mA mA 4 4 60 56 750 1200 550 700 ns ns % % ps ps ps ps
tr5 tf5 dt5 tjsrd5
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V, REF0 VT = 1.5 V, 48M VT = 1.5 V, REF0 VT = 1.5 V, 48M VT = 1.5 V, REF0 VT = 1.5 V, 48M 50 46
55 55 430 790 350 520
Jitter, Absolute1
1 2
tjabs5
-550 -700
Guaranteed by design, not 100% tested in production. Edge displacement of a period relative to a 10-clock-cycle rolling average period.
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ICS9148-111
General Layout Precautions: 1) Use a ground plane on the top routing layer of the PCB in all areas not used by traces. 2) Make all power traces and ground traces as wide as the via pad for lower inductance.
Ferrite Bead VDD
C2 22F/20V Tantalum
1 2
2 C1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
1 3.3V Power Route Ground 2.5V Power Route
C2 22F/20V Tantalum Ferrite Bead VDD
3 4 5 6 7 8
Notes: 1 All clock outputs should have provisions for a 15pf capacitor between the clock output and series terminating resistor. Not shown in all places to improve readability of diagram. 2 Optional crystal load capacitors are recommended. They should be included in the layout but not inserted unless needed.
C1
3.3V Power Route
9 10 11 12 13 14 15 16 17 18 19
Component Values: C1 : Crystal load values determined by user C2 : 22F/20V/D case/Tantalum AVX TAJD226M020R C3 : 15pF capacitor FB = Fair-Rite products 2512066017X1 All unmarked capacitors are 0.01F ceramic
20 21 22 23 24
29 28 27 26 25
Clock Load C3
= Routed Power = Ground Connection Key (component side copper) = Ground Plane Connection = Power Route Connection = Solder Pads = Clock Load
Connections to VDD:
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17
ICS9148-111
SYMBOL A A1 A2 B C D E e H h L N
X
COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100
VARIATIONS AC MIN. .620
D NOM. .625
N MAX. .630 48
SSOP Package
Ordering Information
ICS9148yF-111
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
18
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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